1. A computer has a 256 KByte, 4-way
set associative, write back data cache with block size of 32 Bytes. The
processor sends 32 bit addresses to the cache controller. Each cache tag
directory entry contains, in addition to address tag, 2 valid bits, 1 modified
bit and 1 replacement bit.
The number of bits in the tag field of an address is
(A) 11
(B) 14
(C) 16
(D) 27
Answer: (C)
Explanation:
Number of blocks = Cache-Size/Block-Size
= 256 KB / 32 Bytes = 213
Number of Sets = 213 / 4 = 211
Tag + Set offset + Byte offset = 32
Tag + 11 + 5 = 32
Tag = 16
2. The amount of ROM needed to implement a 4 bit multiplier is
(A) 64 bits
(B) 128 bits
(C) 1 Kbits
(D) 2 Kbits
Answer: (D) 2
Kbits
Explanation: For a 4 bit multiplier, there are 24 * 24
combinations, i.e., 28 combinations.
Also, Output of a 4 bit multiplier is 8 bits.
Thus, the amount of ROM needed = 28 * 8 = 211 = 2048 bits
= 2Kbits
3. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
b. 20 nanoseconds
c. 22 nanoseconds
d. 88 nanoseconds
Ans : 22 nanoseconds
Explanation:
Block size in L1 cache = 4 words
block size in L2 cache = 16 words
Access time for L1 cache = 2 ns
Access time for L2 cache = 20 ns
Access time for main memory = 200 ns
Time taken for a block is transferred from L2 cache to L1 cache
Calculation:
Time taken for a block is transferred from L2 cache to L1 cache =Tt
Tt = Time to Access from L2 cache + Time to store in the L1 cache
Tt = 20ns + 2ns = 22ns
4. A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)?
a. 60 ns
b. 30 ns
c. 150 ns
d. 70 ns
Ans : 60 ns
Effective Memory Access Time = Cache hit ratio*Cache access time + Cache miss*( Cache miss penalty + Memory access time)
= 0.8*(30) + (1 - 0.8)*(30 + 150) ns
= 24 + 0.2*(180) ns = 60 ns
No comments:
Post a Comment
Note: Only a member of this blog may post a comment.